Active Pages

Our group has introduced Active Pages, a page-based model of computation which associates simple functions with each page of memory. For example, an Active Page may contain pixels of an image and support functions to transform and filter those pixels. Implementations of this model have achieved up to 1000X speedups over conventional memory systems on data-intensive applications. Active Page architectures have three key features which distinguish them from other intelligent memory proposals.

First, Active Page memory systems are intended to enhance microprocessor performance in a processor-memory architecture. This is in contrast to designs, such as IRAM, which focus on replacing conventional architectures with single-chip systems. While such systems have great potential for portable personal devices, memory requirements for desktop applications are likely to stay ahead of single-chip capacities.

Second, Active Pages use the same interface as conventional memory systems. Active Page data is modified with conventional memory reads and writes; Active Page functions are invoked through memory-mapped writes. Synchronization is accomplished through user-defined memory locations.

Finally, Active Pages can exploit large amounts of parallelism. A memory system typically contains hundreds to thousands of pages of physical memory. Active Page systems can potentially support simultaneous computations at each of these pages. This page-based computation supports data parallelism similar to supercomputers of the past, but in a ubiquitous technology and for commodity applications.

Faculty

Graduate Students

Undergraduates

Alumni

Publications

Tools