Advance Program for ASPLOS-VIII

Eighth International Conference on Architectural Support for Programming Languages and Operating Systems

October 3-7, 1998.

San Jose, California

http://arch.cs.ucdavis.edu/ASPLOS98

Sponsored by the ACM

SIGARCH -- SIGPLAN -- SIGOPS


Rapid advances in VLSI technology, compilers, operating systems, and computer architecture provide a rich environment for creative system design. Like its predecessors, the eighth ASPLOS conference focuses on the interaction of these technologies.


Saturday, October 3

12:00-6:00 (W1): First Workshop on PC-based System Performance and Analysis
Rich Uhlig, Todd Austin, and Dave Kaeli
http://www.eecs.umich.edu/~uhlig/asplos-pc/


Sunday, October 4

Tutorial 1: Processor Techniques for Exploiting Instruction-Level Parallelism
Sriram Vajapeyam, Indian Inst. of Science, Bangalore
Tutorial 2: The Impact of Database System Configuration on Computer Architecture Performance Evaluation
Kimberly Keeton, UC Berkeley
Tutorial 3: SimOS: The Complete Machine Simulator Environment
Mendel Rosenblum, Stanford University
Tutorial 4: Profiling, Instrumentation, and Profile Based Optimization
Mark Vandevoorde and Robert Cohn, Alpha Design Group, Compaq

Tutorials 1 and 3 are concurrent in the morning (8:30-11:30). Tutorials 2 and 4 are concurrent in the afternoon (1:30-4:30). Tutorial descriptions are available here.


Monday, October 5

8:45 Welcome
9:00-10:30 Compiler Optimizations for Memory
  • Compiler-Controlled Memory
    T. Harvey, K. Cooper, Rice University
  • Segregating Heap Objects by Reference Behavior and Lifetime
    B. Zorn, M. Seidl, Univ. of Colorado
  • Finding a Storage Reuse Pattern for any Legal Loop Schedule
    M. Strout, L. Carter, J. Ferrante, B. Simon, UC San Diego

    11:00-12:30 Speculation and ILP Compilation - 1
  • An Empirical Analysis of Instruction Repetition
    A. Sodani, G. Sohi, Univ. of Wisconsin - Madison
  • Space-Time Scheduling of Instruction-Level Parallelism on a RAW Machine
    W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, S. Amarasinghe, MIT Lab. for Computer Science
  • Data Speculation Support for a Chip Multiprocessor
    L. Hammond, M. Willey, K. Olukotun, Stanford University

    2:00-3:30 I/O Systems

  • VISA: Netstation's Virtual Internet SCSI Adapter
    R. Van Meter, Quantum Corp.; G. Finn, S. Hotz, ISI - Univ. of Southern California
  • Active Disks: Programming Model, Algorithms and Evaluation
    A. Acharya, UC Santa Barbara; M. Uysal, J. Saltz, UMD - College Park
  • A Cost-Effective High-Bandwidth Storage Architecture
    G. Gibson, D. Nagle, K. Amiri, J. Butler, F. Chang, H. Gobioff, C. Hardin, E. Riedel, D. Rochberg, J. Zelenka, Carnegie Mellon University

    4:00-6:00 Caches and Memory Systems

  • Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy
    P. Machanick, P. Salverda, L. Pompe, Univ. of the Witwatersrand, South Africa
  • Dependence Based Prefetching for Linked Data Structures
    A. Roth, A. Moshovos, G. Sohi, Univ. of Wisconsin - Madison
  • Performance Counters and State Sharing Annotations: a Unified Approach to Thread Locality
    Boris Weissman, Int. Computer Science Inst., Berkeley
  • Cache-Conscious Data Placement
    B. Calder, C. Krintz, S. John, UC San Diego; T. Austin, Intel Corp.

    6:00-7:30 Reception


    Tuesday, October 6

    9:00-10:30 Cross-Platform Techniques and Branch Prediction
  • An Out-of-Order Execution Technique for Runtime Binary Translators
    B. Le, Hewlett Packard
  • Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs
    C. Krintz, B. Calder, UC San Diego; H. Lee, B. Zorn, Univ. of Colorado
  • Variable Length Path Branch Prediction
    J. Stark, M. Evers, Y. Patt, Univ. of Michigan - Ann Arbor

    11:00-12:30 Multiprocessor Systems

  • Performance Isolation: Sharing and Isolation in Shared-Memory Multiprocessors
    B. Verghese, Compaq Computer Corp. (WRL); A. Gupta, Microsoft and Stanford Univ.; M. Rosenblum, Stanford Univ.
  • UTLB: A Mechanism for Address Translation on Network Interfaces
    Y. Chen, C. Dubnicki, S. Damianakis, A. Bilas, K. Li, Princeton University
  • Locality-Aware Request Distribution in Cluster-Based Network Servers
    V. Pai, M. Aron, G. Banga, M. Svendsen, P. Druschel, W. Zwaenepoel, Rice University; E. Nahum, IBM TJ Watson

    2:00-3:30 Wild and Crazy Ideas
    Final information.

    4:00-5:30 Cache Analysis

  • Investigating Optimal Local Memory Performance
    O. Temam, Laboratoire PRiSM, Universite Versailles
  • Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity
    S. Ghosh, M. Martonosi, S. Malik, Princeton University
  • Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology
    J. Peir, Y. Lee, Univ. of Florida - Gainesville; W. Hsu, UC Berkeley

    8:00-10:00 Panel Session


    Wednesday, October 7

    9:00-10:30 Speculation and ILP Compilation - 2
  • Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units
    D. Citron, D. Feitelson, Hebrew Univ. of Jerusalem; L. Rudolph, MIT
  • Value Speculation Scheduling for High Performance Processors
    C. Fu, M. Jennings, S. Larin, T. Conte, North Carolina State Univ.
  • An Empirical Study of Decentralized ILP Execution Models
    N. Ranganathan, Intel Corp.; M. Franklin, Univ. of Maryland

    11:00-12:30 Simulation and Performance

  • Fast Out-Of-Order Processor Simulation Using Memoization
    E. Schnarr, J. Larus, Univ. of Wisconsin - Madison
  • A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations
    B. Jacob, Univ. of Maryland; T. Mudge, Univ. of Michigan - Ann Arbor
  • Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors
    P. Ranganathan, Rice University; K. Gharachorloo, Compaq Computer Corp. (WRL); S. Adve, Rice University; L. Barroso, Compaq Computer Corp. (WRL)

    1:30-6:30 (W2): The 3rd Workshop on Interaction between Compilers and Computer Architectures
    Pen-Chung Yew and Gyungho Lee
    http://www-users.cs.umn.edu/~sycho/Workshop98

    Conference Chairs

    General: Dileep Bhandarkar, Intel
    Program: Anant Agarwal, MIT
    Tutorial/Workshops: David R. Kaeli, Northeastern
    Local: Jason Ding and Akhilesh Kumar, Intel
    Finance/Registration: D. N. Jayasimha, Intel
    Publicity: Frederic T. Chong, UC Davis

    Program Committee

    Saman Amarasinghe, MIT
    Prith Banerjee, Northwestern
    Brian Bershad, University of Washington
    Josh Fisher, HP Laboratories
    Maya Gokhale, Sarnoff
    Allan Gottlieb, NYU
    Anoop Gupta, Stanford and Microsoft Research
    Mark Hill, Wisconsin
    Wen-mei Hwu, Illinois
    Randy Katz, UC Berkeley
    John Kubiatowicz, UC Berkeley
    Kathryn S. McKinley, Univ of Massachusetts, Amherst
    Chuck Thacker, Microsoft
    Willy Zwaenepoel, Rice

    Conference Site and Accomodations

    San Jose is conveniently located midway between San Francisco and the Monterey/Carmel area at the sunny southern end of San Francisco Bay. The ocean, the mountains, and many other attractions are just a short drive away.

    Accomodations: The Fairmont Hotel is centrally located in downtown San Jose at 170 South Market Street, across from the Convention Center. Call 408-998-1900 for reservations (mention ASPLOS). Reservations must be made before September 12th to guarantee room availability and rates. Single rooms are $159 and double rooms are $179 per night.

    Transportation: The nearest airport is San Jose International Airport. One can take a taxi (around $12) or a shuttle (South Bay Flyer 888-463-5937; about $6 from San Jose International, $16 from San Francisco International) to the hotel.


    Last updated August 25, 1998
    chong@cs.ucdavis.edu