The continued scaling of silicon technology beyond the 0.25mm generation is characterized by ever more aggressive device technology and the integration of new materials such as copper, low dielectric constant materials, and even SOI substrates to extract even more performance out of the technology. As this exercise becomes more difficult at the technology level, the trend to miniaturization and lower operating voltages permits an ever-increasing degree of functional integration with the potential of dramatic improvements in performance, cost and power at the systems level. Functional integration encompasses both the design and test methodologies, as well as the integration of technologically disparate elements such as logic, analog and memory circuits. This talk will address the key issue of on-chip memory, which typically accounts for over half the real estate on a modern die. We will consider the technology, design, test and application space for on-chip memory using embedded DRAM. We will consider the tradeoffs involved in merging DRAM and Logic. If Logic performance is paramount and if DRAM performance is to be optimized, a logic technology is best suited. In this scenario, the DRAM cell must be designed within the framework of the Logic Design Rules. This results in a cell size that is about 50% larger than the cell in the corresponding DRAM generation. If however, cost is of paramount importance, and manufacturing volumes are comparable to a commodity part, a commodity DRAM technology is better suited. In this case however, logic performance and density will suffer. We will address this question in detail. Finally, a tradeoff between embedded SRAM and eDRAM needs to be made. The cell size reduction of over 6-8 must be reconciled with the increased processing cost of 25-30% that must be amortized over the non-memory portions of the die. We will also consider the impact of RAM performance and array utilzation. The architectural complexity of dealing with refresh, read-write, and test must also be accounted for. When all these issues are considered, eDRAM offers a unique and clear solution for applications that require high logic and memory performance, as well as large amounts of proximate memory.
SUBRAMANIAN S. IYER
Subramanian S. Iyer obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay in 1977, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles in 1978 and 1981 respectively. He joined the IBM T. J. Watson Research Center in 1981 as a Research Staff Member, and was manager of the Exploratory Structures and Devices Group till 1994 when he founded SiBond LLC to develop and make Silicon-on-insulator materials. Since 1997 he has been with the IBM Microelectronics Division, Semiconductor Research and Development Center, where he manages the embedded DRAM development. Dr. Iyer has received two outstanding Technical achievement awards at IBM for the development of the Titanium Salicide process and the fabrication of the first SiGe Heterojunction Bipolar Transistor. In addition he has received 13 Invention plateau awards. He has authored over 150 articles in technical journals and several book chapters. Dr. Iyer is an Adjunct Professor of Electrical Engineering at Columbia University, New York, and a fellow of IEEE.