The 2nd Workshop on Intelligent Memory Systems
In conjunction with ASPLOS-IX, Boston
Massachusetts, November 12, 2000
Preliminary workshop schedule
- 08:30 Opening Remarks
- 08:40 Session 1: Memory Technology
- Invited Talk: Embedded DRAM; Technology and Challenges
Subu Iyer
IBM Microelectronics
- A 64Mbit Mesochronous Hybrid Wave Pipelined Multi-bank DRAM Macro
Junju Ogawa and Mark Horowitz
Fujitsu Laboratories of America and Stanford University
- Software Controlled Reconfigurable On-Chip Memory for High Performance Computing
Hiroshi Nakamura, Masaaki Kondo and Taisuke Boku
University of Tokyo and University of Tsukuba
- 10:15 Break
- 10:45 Session 2: Architecture
- Content-based Prefetching: Initial Results
Robert Cooksey, Dennis Colarelli, and Dirk Grunwald
University of Colorado
- Memory System Support for Dynamic Cacheline Assembly
Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, and John B. Carter
Unversity of Utah
- Adaptively Mapping Code in an Intelligent Memory Architecture
Yan Solihin, Jaejin Lee and Josep Torrellas
Univeristy of Illinois at Urbana-Champaign and Michigan State University
- 12:00 Lunch
- 13:00 Poster session
- 14:00 Session 3: Applications and Operating Systems
- Invited Talk
Mark Snir
IBM Blue Gene
- The Characterization of Date Intensive Memory Workloads on Distributed PIM Architectures
Richard C. Murphy, Peter M. Kogge and Arun Rodrigues
University of Notre Dame
- Memory Management in a PIM-Based Architecture
Mary Hall and Craig Steele
USC Information Sciences Institute
- 15:35 Break
- 16:00 Session 4: Compilers
- Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
David Judd and Katherine Yelick
University of California, Berkeley
- FlexCache: A Framework for Flexible Compiler Generated Data Caching
Csaba Andras Moritz, Matthew Frank and Saman Amarasinghe
MIT
- 16:50 Open-mike session
- 17:20 Closing Remarks
Last updated Oct 16th, 2000
oskin@cs.ucdavis.edu