Large-scale AI training and inference require hundreds of gigabytes to terabytes of DRAM with high peak to average utilization ratios, resulting in overprovisioning. In cloud computing, DRAM constitutes a significant share of the cost. Yet, as shown by recent articles, DRAM is heavily under utilized. Memory disaggregation is a solution to both these problems. With the advent of the CXL protocol, there is renewed interest in designing and optimizing computing systems with disaggregated memory. However, at present, there are limited simulation tools available for exploring the design space and evaluating the performance tradeoffs in computer systems with disaggregated memory.
In this paper, we propose CXL-ClusterSim, a full-system modeling and simulation framework by combining the gem5 simulator for fidelity, with the Structural Simulation Toolkit (SST) for parallel simulation. We outline the challenges in creating this simulation infrastructure and present a design that is scalable, flexible, and reasonably fast to help computer architects to explore the design space of CXL-based disaggregated memory and identify new opportunities for hardware/software codesign and performance optimization.
@misc{goswami2026cxlclustersimmodelingcxlbaseddisaggregated,
title={CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST},
author={Kaustav Goswami and Maryam Babaie and Hoa Nguyen and Venkatesh Akella and Jason Lowe-Power},
year={2026},
eprint={2605.27745},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={https://arxiv.org/abs/2605.27745},
}
Reproducibility in simulation-based computer architecture research requires coordinating artifacts like disk images, kernels, and benchmarks, but existing workflows are inconsistent. We improve gem5, an open-source simulator with over 1600 forks, and gem5 Resources, a centralized repository of over 2000 pre-packaged artifacts, to address these issues. While gem5 Resources enables artifact sharing, researchers still face challenges. Creating custom disk images is complex and timeconsuming, with no standardized process across ISAs, making it difficult to extend and share images. gem5 provides limited guesthost communication features through a set of predefined exit events that restrict researchers’ ability to dynamically control and monitor simulations. Lastly, running simulations with multiple workloads requires researchers to write custom external scripts to coordinate multiple gem5 simulations which creates errorprone and hard-to-reproduce workflows. To overcome this, we introduce several features in gem5 and gem5 Resources. We standardize disk-image creation across x86, ARM, and RISCV using Packer, and provide validated base images with preannotated benchmark suites (NPB, GAPBS). We provide 12 new disk images, 6 new kernels, and over 200 workloads across three ISAs. We refactor the exit event system to a class-based model and introduce hypercalls for enhanced guest-host communication that allows researchers to define custom behavior for their exit events. We also provide a utility to remotely monitor simulations and the gem5-bridge driver for user-space m5 operations. Additionally, we implemented Suites and MultiSim to enable parallel full-system simulations from gem5 configuration scripts, eliminating the need for external scripting. These features reduce setup complexity and provide extensible, validated resources that improve reproducibility and standardization.
@INPROCEEDINGS{11527308,
author={Pai, Kunal and Patel, Harshil and Le, Erin and Krim, Noah and Samani, Mahyar and Bruce, Bobby R. and Lowe-Power, Jason},
booktitle={2026 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
title={Toward Reproducible and Standardized Computer Architecture Simulation with gem5},
year={2026},
volume={},
number={},
pages={184-196},
keywords={Simulation;Timing;Radio access networks;Regional area networks;Kernel;Arm;Computer architecture;Printing;Testing;Booting;gem5;computer architecture;reproducibility},
doi={10.1109/ISPASS69572.2026.00027}}
Memory disaggregation via Compute Express Link (CXL) enables multiple hosts to share remote memory, improving utilization for data-intensive workloads. Today, virtual memory enables process-level isolation on a host and CXL enables host-level isolation. This creates a critical security gap: the absence of process-level memory isolation in shared disaggregated memory.
We present Space-Control, a hardware-software co-design that provides fine-grained, process-level isolation for shared disaggregated memory. Space-Control authenticates execution context in the hardware and enforces access control on every memory access and amortizes lookup times with a small cache. We present Space-Control, a hardware-software co-design that provides fine-grained, process-level isolation for shared disaggregated memory. Space-Control authenticates execution context in the hardware and enforces access control on every memory access and amortizes lookup times with a small cache. Our design allows up to 127 processes running concurrently on 255 hosts to share memory with only 1.56% storage overhead. In a gem5 + Structural Simulation Toolkit (SST) based CXL model, Space-Control incurs minimal performance overhead of 3.3%, making shared disaggregated memory isolation practical.
@misc{goswami2026spacecontrolprocesslevelisolationsharing,
title={Space-Control: Process-Level Isolation for Sharing CXL-based Disaggregated Memory},
author={Kaustav Goswami and Sean Peisert and Venkatesh Akella and Jason Lowe-Power},
year={2026},
eprint={2603.06951},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={https://arxiv.org/abs/2603.06951},
}
As Moore’s Law slows, superconducting electronics offer ultra-low-power, high-speed computation potential. This paper presents the first full-system superconducting architecture modeling in gem5, evaluating superconducting cores, caches, and interconnects under realistic workloads. We extend gem5 with cryogenic semiconductor (4 GHz) and superconducting (100 GHz) RISC-V cores and multi-level caches, evaluating RISC-V benchmarks and SPEC CPU2006 applications. We also integrate SRNoC, a superconducting interconnect, with the NOVA graph accelerator. Results show superconducting cores and caches achieve up to 24 × speedup for compute-intensive workloads, but memory-intensive applications are bottlenecked by room-temperature DRAM (1.2 × improvement). High cache bandwidth requirements (800 GB/s) present design challenges. SRNoC provides 35-73 × energy efficiency gains for narrow data paths but 1246 × slowdown for wide data communication. Therefore, superconducting technology suits domain-specific accelerators better than general-purpose computing, with performance dependent on workload memory access patterns and data widths.
@inproceedings{10.1145/3731599.3769278,
author = {Pai, Kunal and Samani, Mahyar and Nand, Anusheel and Lowe-Power, Jason},
title = {Implications of Full-System Modeling for Superconducting Architectures},
year = {2025},
isbn = {9798400718717},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3731599.3769278},
doi = {10.1145/3731599.3769278},
abstract = {As Moore's Law slows, superconducting electronics offer ultra-low-power, high-speed computation potential. This paper presents the first full-system superconducting architecture modeling in gem5, evaluating superconducting cores, caches, and interconnects under realistic workloads. We extend gem5 with cryogenic semiconductor (4 GHz) and superconducting (100 GHz) RISC-V cores and multi-level caches, evaluating RISC-V benchmarks and SPEC CPU2006 applications. We also integrate SRNoC, a superconducting interconnect, with the NOVA graph accelerator. Results show superconducting cores and caches achieve up to 24 × speedup for compute-intensive workloads, but memory-intensive applications are bottlenecked by room-temperature DRAM (1.2 × improvement). High cache bandwidth requirements (800 GB/s) present design challenges. SRNoC provides 35-73 × energy efficiency gains for narrow data paths but 1246 × slowdown for wide data communication. Therefore, superconducting technology suits domain-specific accelerators better than general-purpose computing, with performance dependent on workload memory access patterns and data widths.},
booktitle = {Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis},
pages = {1484–1490},
numpages = {7},
keywords = {superconducting electronics, cryogenic computing, gem5, full-system},
series = {SC Workshops '25}
}
We propose a scalable graph processing hardware accelerator called NOVA that is based on a novel vertex management architecture that decouples the execution of reduction and propagation operations in the popular vertex-centric graph processing paradigm. This allows us to store the working set in off-chip memory and utilize the available on-chip memory as a buffer to hide the latency of DRAM accesses instead of a traditional cache. This overcomes one of the key drawbacks of almost all prior works which require temporal partitioning of graphs to scale to large graphs. We develop a cycle-accurate model of the architecture in gem5 and demonstrate that NOVA exhibits near-perfect weak and strong scaling while scaling to large graphs by spatially tiling multiple nodes. In addition, our simulations show that NOVA is 2.35x better that a state-of-the-art graph accelerator (PolyGraph) while using a fraction of the on-chip memory on a synthetic graph with 134M vertices and over 2.14B edges.
@article{babaie2024tdram,
author = {Marjan Fariborz and Mahyar Samani and Austin York and SJ Ben Yoo and Jason Lowe-Power and Venkatesh Akella},
title = {NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing},
year = {2025},
url = {https://doi.org/10.1109/HPCA61900.2025.00072},
doi = {10.1109/HPCA61900.2025.00072},
}
As SRAM-based caches are hitting a scaling wall, manufacturers are integrating DRAM-based caches into system designs to continue increasing cache sizes. While DRAM caches can improve the performance of memory systems, existing DRAM cache designs suffer from high miss penalties, wasted data movement, and interference between misses and demands. In this paper, we propose TDRAM, a novel DRAM microarchitecture tailored for caching. TDRAM enhances existing DRAM, such as HBM3, by adding small, low-latency mats to store tags and metadata on the same die as the data mats. These mats enable tag and data access in lockstep, in-DRAM tag comparison, and conditional data response based on the comparison result (reducing wasted data transfers), akin to SRAM cache mechanisms. TDRAM further optimizes hit and miss latencies through opportunistic early tag probing. Moreover, TDRAM introduces a flush buffer to store conflicting dirty data on write misses, eliminating data bus turnaround delays on write demands. We evaluate TDRAM in a full-system simulation using a set of HPC workloads with large memory footprints, showing that TDRAM, on average, provides 2.65× faster tag checks, 1.23× speedup, and 21% less energy consumption compared to state-of-the-art commercial and research designs.
Maryam Babaie, Ayaz Akram, Wendy Elsasser, Brent Haukness, Michael R. Miller, Taeksang Song, Thomas Vogelsang, Steven C. Woo, and Jason Lowe-Power, “TDRAM: Tag-enhanced DRAM for Efficient Caching,” arXiv preprint arXiv:2404.14617, 2024. doi: 10.48550/arXiv.2404.14617.
@article{babaie2024tdram,
author = {Maryam Babaie and Ayaz Akram and Wendy Elsasser and Brent Haukness and Michael R. Miller and Taeksang Song and Thomas Vogelsang and Steven C. Woo and Jason Lowe-Power},
title = {TDRAM: Tag-enhanced DRAM for Efficient Caching},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2404.14617},
doi = {10.48550/arXiv.2404.14617},
eprint={2404.14617},
archivePrefix={arXiv},
primaryClass={cs.AR}
}
This paper explores the potential of cryogenic semiconductor computing and superconductor electronics as promising alternatives to traditional semiconductor devices. As semiconductor devices face challenges such as increased leakage currents and reduced performance at higher temperatures, these novel technologies offer high performance and low power computation. Conventional semiconductor electronics operating at cryogenic temperatures (below -150°C or 123.15 K) can benefit from reduced leakage currents and improved electron mobility. On the other hand, superconductor electronics, operating below 10 K, allow electrons to flow without resistance, offering the potential for ultra-low-power, high-speed computation. This study presents a comprehensive performance modeling and analysis of these technologies and provides insights into their potential benefits and limitations. We implement models of in-order and out-of-order cores operating at high clock frequencies associated with superconductor electronics and cryogenic semiconductor computing in gem5. We evaluate the performance of these components using workloads representative of real-world applications like NPB, SPEC CPU2006, and GAPBS. Our results show the potential speedups achievable by these components and the limitations posed by cache bandwidth. This work provides valuable insights into the performance implications and design trade-offs associated with cryogenic and superconductor technologies, laying the foundation for future research in this field using gem5.
Kunal Pai, Anusheel Nand, Jason Lowe-Power, “Potential and Limitations of High-Frequency Cores and Caches,” arXiv preprint arXiv:2408.03308, 2024. doi: 10.48550/arXiv.2408.03308.
@misc{pai2024potentiallimitationhighfrequencycores,
title={Potential and Limitation of High-Frequency Cores and Caches},
author={Kunal Pai and Anusheel Nand and Jason Lowe-Power},
year={2024},
eprint={2408.03308},
archivePrefix={arXiv},
primaryClass={cs.AR},
url={https://arxiv.org/abs/2408.03308},
}
We propose a new framework called CachedArrays and a set of APIs to address the data tiering problem in large scale heterogeneous and disaggregated memory systems. The proposed framework operates at a variable size object granularity and allows the programmer to specify semantic hints about future use of data via a Policy API, which are used by a Data Manager to choose when and where to place a particular data object using a data management API, thus bridging the semantic gap between the programmer and the platform-specific hardware details, and optimizing overall performance. We evaluate the proposed framework on a real hardware platform with terabytes of memory consisting of NVRAM and DRAM on large scale ML training workloads such CNNs that exhibit different data access and usage patterns. We show that CachedArrays outperforms hardware caches, and can exploit many of the algorithmic-specific optimizations of prior works.
CachedEmbeddings builds on top of CachedArrays.
@inproceedings{hildebrand24cachedarrays,
author = {Hildebrand, Mark and Lowe-Power, Jason and Akella, Venkatesh},
title = { {CachedArrays}: Optimizing Data Movement for Heterogeneous Memory Systems},
year = {2024},
url = {https://doi.org/10.1109/IPDPS57955.2024.00055},
doi = {10.1109/IPDPS57955.2024.00055},
booktitle = {Proceeding of the 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}
}
Graphs are essential for representing relationships in various domains, driving modern AI applications such as graph analytics and neural networks across science, engineering, cybersecurity, transportation, and economics. However, the size of modern graphs are rapidly expanding, posing challenges for traditional CPUs and GPUs in meeting real-time processing demands. As a result, hardware accelerators for graph processing have been proposed. However, the largest graphs that can be handled by these systems is still modest often targeting Twitter graph (1.4B edges approximately). This paper aims to address this limitation by developing a graph accelerator capable of terascale graph processing. Scale out architectures, architectures where nodes are replicated to expand to larger datasets, are natural for handling larger graphs. We argue that this approach is not appropriate for very large-scale graphs because it leads to under utilization of both memory resources and compute resources. Additionally, vertex and edge processing have different access patterns. Communication overheads also pose further challenges in designing scalable architectures. To overcome these issues, this paper proposes TEGRA, a scale-up architecture for terascale graph processing. TEGRA leverages a composable computing system with disaggregated resources and a communication architecture inspired by Active Messages. By employing direct communication between cores and optimizing memory interconnect utilization, TEGRA effectively reduces communication overhead and improves resource utilization, therefore enabling efficient processing of terascale graphs.
William Shaddix, Mahyar Samani, Marjan Fariborz, S.J. Ben Yoo, Jason Lowe-Power, and Venkatesh Akella, “TEGRA – Scaling Up Terascale Graph Processing with Disaggregated Computing,” arXiv preprint arXiv:2404.03155, 2024. doi: 10.48550/arXiv.2404.03155.
@article{shaddix2024tegra,
author = {William Shaddix and Mahyar Samani and Marjan Fariborz and S.J. Ben Yoo and Jason Lowe-Power and Venkatesh Akella},
title = {TEGRA -- Scaling Up Terascale Graph Processing with Disaggregated Computing},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2404.03155},
doi = {10.48550/arXiv.2404.03155},
eprint={2404.03155},
archivePrefix={arXiv},
primaryClass={cs.AR}
}
Mobile app developers often rely on cameras to implement rich features. However, giving apps unfettered access to the mobile camera poses a privacy threat when camera frames capture sensitive information that is not needed for the app’s functionality. To mitigate this threat, we present Aragorn, a novel privacy-enhancing mobile camera system that provides fine grained control over what information can be present in camera frames before apps can access them. Aragorn automatically sanitizes camera frames by detecting regions that are essential to an app’s functionality and blocking out everything else to protect privacy while retaining app utility. Aragorn can cater to a wide range of camera apps and incorporates knowledge distillation and crowdsourcing to extend robust support to previously unsupported apps. In our evaluations, we see that, with no degradation in utility, Aragorn detects credit cards with 89\% accuracy and faces with 100\% accuracy in context of credit card scanning and face recognition respectively. We show that Aragorn’s implementation in the Android camera subsystem only suffers an average drop of 0.01 frames per second in frame rate. Our evaluations show that the overhead incurred by Aragorn to system performance is reasonable.
Hari Venugopalan, Zainul Abi Din, Trevor Carpenter, Jason Lowe-Power, Samuel T. King, and Zubair Shafiq. 2024. Aragorn: A Privacy-Enhancing System for Mobile Cameras. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 7, 4, Article 181 (December 2023), 31 pages. https://doi.org/10.1145/3631406
@article{Venugopalan2024aragorn,
author = {Venugopalan, Hari and Din, Zainul Abi and Carpenter, Trevor and Lowe-Power, Jason and King, Samuel T. and Shafiq, Zubair},
title = {Aragorn: A Privacy-Enhancing System for Mobile Cameras},
year = {2024},
issue_date = {December 2023},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
volume = {7},
number = {4},
url = {https://doi.org/10.1145/3631406},
doi = {10.1145/3631406},
journal = {Proc. ACM Interact. Mob. Wearable Ubiquitous Technol.},
month = {jan},
articleno = {181},
numpages = {31},
keywords = {Knowledge Distillation, Object Detection}
}