Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing

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Abstract

In this paper we propose a microarchitectural technique called Constant Average Power Processing (CAPP) that reduces the execution time of parallel programs by dynamically detecting the power slack at runtime and directing it to specific core(s) that are the bottleneck at any given time. The key insight of this work is that by sensing the current, communicating it to the global controller and adjusting the cores’ frequencies, it is possible to maintain a constant power level in a distributed and scalable manner. We evaluate the potential benefits and scalability of the proposed technique on a set of synthetic benchmarks and compare the results with related work such as Running Average Power Limit (RAPL)..

Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew Farrens and Venkatesh Akella, “Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing,” 2017 IEEE International Conference on Computer Design (ICCD), Boston, MA, 2017, pp. 649-652. doi: 10.1109/ICCD.2017.113

@inproceedings{capp:Straube:2017, 
    author={Kramer Straube and Christopher Nitta and Raj Amirtharajah and Matthew Farrens and Venkatesh Akella}, 
    booktitle={2017 IEEE International Conference on Computer Design (ICCD)}, 
    title={Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing}, 
    year={2017}, 
    pages={649-652}, 
    doi={10.1109/ICCD.2017.113}, 
    ISSN={1063-6404}, 
    month={Nov},
}

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