Integrating Cycle Accurate Chisel Models with gem5’s System Simulation

Poster Download

Abstract

Computing systems are becoming more heterogeneous with SoC that include CPUs, programmable accelerators, non-programmable accelerators, and memory. Software simulation of computing systems is an important step in the design process, and simulation accuracy is required for meaningful results. Tools such as gem5 allow large design-space exploration due to its flexible configuration and high-level C++ models of many different system components. However, gem5 is only cycle-level not cycle-accurate. On the other hand, Chisel provides cycle-accurate simulation models of hardware components via FIRRTL interpretation and Verilator via the Verilog backend. By combining gem5’s system simulation with cycle-accurate models generated from Chisel, it will enable researchers to perform system-level explorations with cycle-accurate components. This poster presents our initial design and preliminary results from embedding Chisel HDL components in the gem5 simulator. By embedding Chisel-generated components in gem5, researchers and designers can concentrate on their sub-module without having to implement all other system components in Chisel or another HDL. Additionally, leveraging gem5’s full system capability allows researchers and developers to evaluate new hardware designs in a realistic system running a real operating system and all other system details.

Citation

@misc{poster:Ganjeloo:2018
    author = {Nima Ganjehloo, Venkatesh Akella, Jason Lowe-Power},
    school = {University of California, Davis},
    year = {2018},
    title = {Integrating Cycle Accurate Chisel Models with gem5's System Simulation},
}

Updated: