FlexCPU: A Configurable Out-of-Order CPU Abstraction

Bradley Wang, Ayaz Akram, Jason Lowe-Power ISPASS 2019.

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We present FlexCPU, a new software model for CPU performance integrated into gem5. FlexCPU combines the benefits of trace-based models with execute-in-execute semantics which leads to more accurate simulation of multithreaded and full-system applications. Our design is heavily inspired by dataflow models, and it reduces modern out-of-order techniques to abstracted parameterized constraints. FlexCPU can be configured to match the behaviors of modern general purpose CPUs and used for limit studies. By reducing CPU behaviors to reasonable abstractions and stages, FlexCPU is simpler to understand and easier to extend than other execute-in-execute CPU models. We show that FlexCPU can achieve the maximum theoretical ILP for most workloads and show a case study of using FlexCPU to model multiple processor architectures.


  author={B. {Wang} and A. {Akram} and J. {Lowe-Power}},
  booktitle={2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}, 
  title={FlexCPU: A Configurable Out-of-Order CPU Abstraction},