Enabling Design Space Exploration for RISC-V Secure Compute Environments

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Simulating a TEE in gem5

In this work, we implemented the RISC-V hardware required to run the Keystone TEE in gem5.

gem5 now supports executing the Keystone security monitor (SM) and Eyrie runtime. This will enable future research on hardware support for secure architectures!

Citation

Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021). With ISCA 2021.

@inproceedings{akram2021gem5tee,
  title={Enabling Design Space Exploration for  Secure Compute Environments},
  author={Ayaz Akram and Venkatesh Akella and Sean Peisert and Jason Lowe-Power},
  booktitle={Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021)},
  year={2021}
}