Toward Reproducible and Standardized Computer Architecture Simulation with gem5

Paper arXiv

Reproducibility in simulation-based computer architecture research requires coordinating artifacts like disk images, kernels, and benchmarks, but existing workflows are inconsistent. We improve gem5, an open-source simulator with over 1600 forks, and gem5 Resources, a centralized repository of over 2000 pre-packaged artifacts, to address these issues. While gem5 Resources enables artifact sharing, researchers still face challenges. Creating custom disk images is complex and timeconsuming, with no standardized process across ISAs, making it difficult to extend and share images. gem5 provides limited guesthost communication features through a set of predefined exit events that restrict researchers’ ability to dynamically control and monitor simulations. Lastly, running simulations with multiple workloads requires researchers to write custom external scripts to coordinate multiple gem5 simulations which creates errorprone and hard-to-reproduce workflows. To overcome this, we introduce several features in gem5 and gem5 Resources. We standardize disk-image creation across x86, ARM, and RISCV using Packer, and provide validated base images with preannotated benchmark suites (NPB, GAPBS). We provide 12 new disk images, 6 new kernels, and over 200 workloads across three ISAs. We refactor the exit event system to a class-based model and introduce hypercalls for enhanced guest-host communication that allows researchers to define custom behavior for their exit events. We also provide a utility to remotely monitor simulations and the gem5-bridge driver for user-space m5 operations. Additionally, we implemented Suites and MultiSim to enable parallel full-system simulations from gem5 configuration scripts, eliminating the need for external scripting. These features reduce setup complexity and provide extensible, validated resources that improve reproducibility and standardization.

Citation

@INPROCEEDINGS{11527308,
  author={Pai, Kunal and Patel, Harshil and Le, Erin and Krim, Noah and Samani, Mahyar and Bruce, Bobby R. and Lowe-Power, Jason},
  booktitle={2026 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)}, 
  title={Toward Reproducible and Standardized Computer Architecture Simulation with gem5}, 
  year={2026},
  volume={},
  number={},
  pages={184-196},
  keywords={Simulation;Timing;Radio access networks;Regional area networks;Kernel;Arm;Computer architecture;Printing;Testing;Booting;gem5;computer architecture;reproducibility},
  doi={10.1109/ISPASS69572.2026.00027}}