A Model for Scalable and Balanced Accelerators for Graph Processing

Local Download IEEE Xplore Link

Designing a graph processing system that can scale to graph sizes that are orders of magnitude larger than what is possible on a single accelerator requires a careful codesign of accelerator memory bandwidth and capacity, the interconnect bandwidth between accelerators, and the overall system architecture. We present a high-level bottleneck-analysis model for design and evaluation of scalable and balanced accelerators for graph processing. We show several applications of this model including how to choose the right mix of different memory types, network topology, network bisection bandwidth, and system-level architecture to match the access patterns and capacity requirements of different data structures for a given graph and a performance target.

Citation

M. Fariborz, M. Samani, T. O’Neill, J. Lowe-Power, S. J. B. Yoo and V. Akella, “A Model for Scalable and Balanced Accelerators for Graph Processing,” in IEEE Computer Architecture Letters, vol. 21, no. 2, pp. 149-152, 1 July-Dec. 2022, doi: 10.1109/LCA.2022.3215489.

@ARTICLE{fariobrz2022model,
  author={Fariborz, Marjan and Samani, Mahyar and O'Neill, Terry and Lowe-Power, Jason and Yoo, S.J. Ben and Akella, Venkatesh},
  journal={IEEE Computer Architecture Letters}, 
  title={A Model for Scalable and Balanced Accelerators for Graph Processing}, 
  year={2022},
  volume={21},
  number={2},
  pages={149-152},
  doi={10.1109/LCA.2022.3215489}}