The increasing growth of applications’ memory demands has led the CPU vendors to deploy diverse memory technologies either within the same package such as heterogenous memory systems, or in disaggregated form through local or remote memory nodes. As these new memory technologies emerge, conventional memory management should be reconsidered to better meet the applications memory requirements. However, there is not a suitable model available in the community to accurately study these new systems. In this work we describe our contribution toward a cycle-level analysis model of heterogenous memories in gem5 simulator. We believe this work enables the community to perform a design space exploration for the next generation of memory systems.