NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing

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We propose a scalable graph processing hardware accelerator called NOVA that is based on a novel vertex management architecture that decouples the execution of reduction and propagation operations in the popular vertex-centric graph processing paradigm. This allows us to store the working set in off-chip memory and utilize the available on-chip memory as a buffer to hide the latency of DRAM accesses instead of a traditional cache. This overcomes one of the key drawbacks of almost all prior works which require temporal partitioning of graphs to scale to large graphs. We develop a cycle-accurate model of the architecture in gem5 and demonstrate that NOVA exhibits near-perfect weak and strong scaling while scaling to large graphs by spatially tiling multiple nodes. In addition, our simulations show that NOVA is 2.35x better that a state-of-the-art graph accelerator (PolyGraph) while using a fraction of the on-chip memory on a synthetic graph with 134M vertices and over 2.14B edges.

Citation

@article{babaie2024tdram,
  author       = {Marjan Fariborz and Mahyar Samani and Austin York and SJ Ben Yoo and Jason Lowe-Power and Venkatesh Akella},
  title        = {NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing},
  year         = {2025},
  url          = {https://doi.org/10.1109/HPCA61900.2025.00072},
  doi          = {10.1109/HPCA61900.2025.00072},
}