A Cycle-level Unified DRAM Cache Controller Model in gem5

Maryam Babaie, Ayaz Akram, Jason Lowe-Power ISCA 2022: The 4th gem5 Tutorial and User’s Workshop.

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The increasing growth of applications’ memory demands has led the CPU vendors to deploy large DRAM caches, backed by large non-volatile memories like Intel Optane (e.g., Intel’s Cascade Lake). Previous work has explored many aspects of DRAM cache design in simulation such as the caching granularity, dram cache tag placement, etc. to improve performance. However, these works do not provide an open-source DRAM cache modeling plat-form for a detailed micro-architectural and timing analysis. In this presentation we will describe a cycle-level unified DRAM cache and main memory controller (UDCC) for gem5. The protocol is inspired by the actual hardware providing DRAM cache, such as Intel’s Cascade Lake, in which a DRAM cache is backed by an NVRAM as the off-chip main memory sharing the same bus. We leverage the cycle-level DRAM and NVRAM models in gem5.