Architecture simulators are a common and powerful tool in computer architecture research. It is important that results reported by simulators are trustworthy. gem5 is a well known architectural simulator used by academia and industry. We present our methodology and tools for evaluating gem5’s memory subsystem components and the results of our validation of gem5’s current memory system components. We have validated the accuracy of DDR models in gem5 and report significant difference between gem5 and our reference for HBM models. In addition, we have validated the functional correctness and accuracy of cache models in gem5. Lastly, we observe a 10% difference between gem5 and real hardware in our random access benchmark.