Integrating Cycle Accurate Chisel Models with gem5’s System Simulation

Nima Ganjehloo, Jason Lowe-Power, Venkatesh Akella. CCC 2018.

Poster Download

Computing systems are becoming more heterogeneous with SoCs that include CPUs, programmable accelerators, non-programmable accelerators, and memory. Software simulation of computing systems is an important step in the design process, and simulation accuracy is required for meaningful results. Tools such as gem5 allow large design-space exploration due to its flexible configuration and high-level C++ models of many different system components. However, gem5 is only cycle-level not cycle-accurate.

On the other hand, Chisel provides cycle-accurate simulation models of hardware components via FIRRTL interpretation and Verilator via the Verilog backend. By combining gem5’s system simulation with cycle-accurate models generated from Chisel, it will enable researchers to perform system-level explorations with cycle-accurate components.

This poster presents our initial design and preliminary results from embedding Chisel HDL components in the gem5 simulator. By embedding Chisel-generated components in gem5, researchers and designers can concentrate on their sub-module without having to implement all other system components in Chisel or another HDL. Additionally, leveraging gem5’s full system capability allows researchers and developers to evaluate new hardware designs in a realistic system running a real operating system and all other system details.

Benefits of gem5’s cycle-level simulation

gem5 is a popular cycle-level system simulation infrastructure. The gem5 paper has been cited over 2,500 times since 2011, and gem5 is used in academic papers, industry simulation, and teaching computer architecture. gem5 is highly-configurable with a Python interface for building complex real-world systems. It contains models for many ISAs (RISC-V, x86, ARM, and others), many memory system models (DDR3, DDR4, HBM, GDDR5, etc.), a configurable cache coherence model, and accelerator models.

gem5 is only cycle-level, not cycle-accurate, which presents tradeoffs. Its models are written in event-driven C++ which models cycles, but is not a direct representation of a hardware implementation. These models are often faster to simulate than their cycle-accurate counterparts, but they are not as accurate. Another benefit of high-level C++ models is that they are easier to write, modify, and understand than implementations of the hardware written in HDL languages.

Benefits of Chisel and cycle-accurate models

On the other hand, models generated from Chisel descriptions of hardware are cycle accurate. These models more accurately represent real hardware implementations than the high-level C++ models in gem5. Additionally, using HDL allows construction of power models that are more accurate. These detailed models allow researchers and designers to investigate detailed design questions like microarchitectural optimizations that are not appropriate to investigate with gem5’s higher-level models.

gem5+Chisel Implementation

We investigate two ways to integrate hardware described in Chisel into gem5. First, we use gem5’s current support for SystemC models to integrate the Chisel-generated Verilog into gem5 by using Verilator. By providing a Verilator interface to gem5, we not only support Chisel, but also any hardware written in Verilog.

Second, we are investigating creating a new FIRRTL backend that generates gem5-compatible hardware models. This method is less flexible than using Verilator since we are constrained to using only Chisel models, but we believe it may allow higher performance models by working at a higher abstraction level.

The key technical challenges will be designing the interface between Verilog/FIRRTL and gem5. We are initially evaluating using memory ports as the main interface. We will release our gem5+Chisel infrastructure as an open source add-on to gem5 on github (, and we will contribute our changes upstream to both gem5 and Chisel/FIRRTL.

gem5+Chisel evaluation

We integrate two different Chisel components into gem5 to evaluate the feasibility of our design: a simple accelerator and a full-fledged RISC-V core. We start by integrating a simple out-of-core accelerator to perform a “daxpy” computation. We directly compare this to a gem5 model of the daxpy accelerator and show more realistic results with the Chisel-based model.

We also integrate a full RISC-V core based on the RocketChip design. We compare the accuracy of gem5+Chisel with the Verilator model of the RocketChip SoC and gem5’s out of order CPU model. We also evaluate the performance of gem5+Chisel compared to Verilator and gem5.


Nima Ganjehloo, Venkatesh Akella, Jason Lowe-Power. Integrating Cycle Accurate Chisel Models with gem5’s System Simulation. Chisel Community Conference. 2018.

    author = {Nima Ganjehloo, Venkatesh Akella, Jason Lowe-Power},
    school = {University of California, Davis},
    year = {2018},
    title = {Integrating Cycle Accurate Chisel Models with gem5's System Simulation},
    booktitle = {Chisel Community Conference}