Implications of Full-System Modeling for Superconducting Architectures

Paper

As Moore’s Law slows, superconducting electronics offer ultra-low-power, high-speed computation potential. This paper presents the first full-system superconducting architecture modeling in gem5, evaluating superconducting cores, caches, and interconnects under realistic workloads. We extend gem5 with cryogenic semiconductor (4 GHz) and superconducting (100 GHz) RISC-V cores and multi-level caches, evaluating RISC-V benchmarks and SPEC CPU2006 applications. We also integrate SRNoC, a superconducting interconnect, with the NOVA graph accelerator. Results show superconducting cores and caches achieve up to 24 × speedup for compute-intensive workloads, but memory-intensive applications are bottlenecked by room-temperature DRAM (1.2 × improvement). High cache bandwidth requirements (800 GB/s) present design challenges. SRNoC provides 35-73 × energy efficiency gains for narrow data paths but 1246 × slowdown for wide data communication. Therefore, superconducting technology suits domain-specific accelerators better than general-purpose computing, with performance dependent on workload memory access patterns and data widths.

Citation

@inproceedings{10.1145/3731599.3769278,
  author = {Pai, Kunal and Samani, Mahyar and Nand, Anusheel and Lowe-Power, Jason},
  title = {Implications of Full-System Modeling for Superconducting Architectures},
  year = {2025},
  isbn = {9798400718717},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3731599.3769278},
  doi = {10.1145/3731599.3769278},
  abstract = {As Moore's Law slows, superconducting electronics offer ultra-low-power, high-speed computation potential. This paper presents the first full-system superconducting architecture modeling in gem5, evaluating superconducting cores, caches, and interconnects under realistic workloads. We extend gem5 with cryogenic semiconductor (4 GHz) and superconducting (100 GHz) RISC-V cores and multi-level caches, evaluating RISC-V benchmarks and SPEC CPU2006 applications. We also integrate SRNoC, a superconducting interconnect, with the NOVA graph accelerator. Results show superconducting cores and caches achieve up to 24 × speedup for compute-intensive workloads, but memory-intensive applications are bottlenecked by room-temperature DRAM (1.2 × improvement). High cache bandwidth requirements (800 GB/s) present design challenges. SRNoC provides 35-73 × energy efficiency gains for narrow data paths but 1246 × slowdown for wide data communication. Therefore, superconducting technology suits domain-specific accelerators better than general-purpose computing, with performance dependent on workload memory access patterns and data widths.},
  booktitle = {Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis},
  pages = {1484–1490},
  numpages = {7},
  keywords = {superconducting electronics, cryogenic computing, gem5, full-system},
  series = {SC Workshops '25}
}