Heterogeneous Memory
Due to technological changes such as the end of Moore’s Law, the end of Dennard Scaling, and an explosion in data, computing systems are becoming more heterogeneous. However, the underlying hardware and software for these systems were developed for homogeneous systems, and directly applying current techniques to heterogeneous system results in poor usability, poor performance, or both. This proposal specifically focuses on improving the software interfaces through new hardware mechanisms for heterogeneous memory systems. New memory technologies are proliferating (e.g., HBM, HMC, PCM, 3D-XPoint, ReRAM, and disaggregated memory), and these new memory technologies have differences in latency, bandwidth, cost, and other new design parameters such as persistence and asymmetric read and write times. Because of these changing technological constraints, future systems are likely to be deeply heterogeneous, combining many different memory technologies. Thus, it is time to redesign the memory hierarchy to accommodate heterogeneous memory systems.
Related publications
Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems
Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella High Performance Computing: 38th International Conference, ISC High Performance 2023.
HammerSim: A Tool to Model Rowhammer
Kaustav Goswami, Ayaz Akram, Hari Venugopalan, Jason Lowe-Power, Young Architect Workshop at ASPLOS 2023.
Validating gem5’s Memory Components
Mahyar Samani, Jason Lowe-Power, gem5 workshop at ISCA 2022.
A Cycle-level Unified DRAM Cache Controller Model in gem5
Maryam Babaie, Ayaz Akram, Jason Lowe-Power ISCA 2022: The 4th gem5 Tutorial and User’s Workshop.
Toward High-Fidelity Heterogeneous Memory System Modeling in gem5
Maryam Babaie, Ayaz Akram, Jason Lowe-Power ModSim 2022: Workshop on Modeling & Simulation of Systems and Applications
Rethinking the Management Techniques in Emerging Memory Systems
Maryam Babaie, Ayaz Akram, Jason Lowe-Power MICRO 2022: The 8th CWIDCA Workshop.
Modeling HBM2 Memory Controller
Ayaz Akram, Maryam Babaie, Wendy Elsasser, Jason Lowe-Power. The 4th gem5 Users’ Workshop associated with ISCA 2022.
LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads
Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-min yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, S. J. Ben Yoo ISC-HPC 2022.
A Case Against Hardware Managed DRAM Caches for NVRAM based Systems
Best paper nominee Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella 2021 IEEE International Symposium on Performance Analysis of System...
Investigating Hardware Caches for Terabyte-scale NVDIMMs
Julian T. Angeles, Mark Hildebrand, Venkatesh Akella, Jason Lowe-Power 12TH Annual Non-volatile Memories Workshop (NVMW 2021) 2021.
AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming
Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella 25th International Conference on Architectural Support for Programming Languages and Operating Systems (...
Filtering Translation Bandwidth with Virtual Caching
Hongil Yoon, Jason Lowe-Power, Gurindar S. Sohi. ASPLOS 2018.
When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads
Jason Lowe-Power, Mark D. Hill, David A. Wood. BPOE Workshop with ASPLOS 2016.
Supporting x86-64 address translation for 100s of GPU lanes
Jason Power, Mark D. Hill,, David A. Wood. HPCA 2014.
Heterogeneous system coherence for integrated CPU-GPU systems
Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood MICRO 2013.
Funding
This work is supported by Lowe-Power’s CAREER Award, NSF CNS-2144883, NSF CNS-2225882, NSF CSR-1850566, Lowe-Power’s Google Research Scholar Award, and the Intel Corporation.