Heterogeneous Memory

Cross-layer rethinking of the memory hierarchy for heterogeneous systems

Due to technological changes such as the end of Moore’s Law, the end of Dennard Scaling, and an explosion in data, computing systems are becoming more heterogeneous. However, the underlying hardware and software for these systems were developed for homogeneous systems, and directly applying current techniques to heterogeneous system results in poor usability, poor performance, or both. This proposal specifically focuses on improving the software interfaces through new hardware mechanisms for heterogeneous memory systems. New memory technologies are proliferating (e.g., HBM, HMC, PCM, 3D-XPoint, ReRAM, and disaggregated memory), and these new memory technologies have differences in latency, bandwidth, cost, and other new design parameters such as persistence and asymmetric read and write times. Because of these changing technological constraints, future systems are likely to be deeply heterogeneous, combining many different memory technologies. Thus, it is time to redesign the memory hierarchy to accommodate heterogeneous memory systems.


This work is supported by Lowe-Power’s CAREER Award, NSF CNS-2144883, NSF CNS-2225882, NSF CSR-1850566, Lowe-Power’s Google Research Scholar Award, and the Intel Corporation.