Heterogeneous Memory

Cross-layer rethinking of the memory hierarchy for heterogeneous systems

Due to technological changes such as the end of Moore’s Law, the end of Dennard Scaling, and an explosion in data, computing systems are becoming more heterogeneous. However, the underlying hardware and software for these systems were developed for homogeneous systems, and directly applying current techniques to heterogeneous system results in poor usability, poor performance, or both. This proposal specifically focuses on improving the software interfaces through new hardware mechanisms for heterogeneous memory systems. New memory technologies are proliferating (e.g., HBM, HMC, PCM, 3D-XPoint, ReRAM, and disaggregated memory), and these new memory technologies have differences in latency, bandwidth, cost, and other new design parameters such as persistence and asymmetric read and write times. Because of these changing technological constraints, future systems are likely to be deeply heterogeneous, combining many different memory technologies. Thus, it is time to redesign the memory hierarchy to accommodate heterogeneous memory systems.

Funding

This work is supported by Lowe-Power’s CAREER Award, NSF CNS-2144883, NSF CNS-2225882, NSF CSR-1850566, Lowe-Power’s Google Research Scholar Award, and the Intel Corporation.

Heterogeneous Memory

CachedArrays: Optimizing Data Movement for Heterogeneous Memory Systems

TEGRA – Scaling Up Terascale Graph Processing with Disaggregated Computing

TDRAM: Tag-enhanced DRAM for Efficient Caching

Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems

HammerSim: A Tool to Model Rowhammer

Validating gem5’s Memory Components

A Cycle-level Unified DRAM Cache Controller Model in gem5

Toward High-Fidelity Heterogeneous Memory System Modeling in gem5

Rethinking the Management Techniques in Emerging Memory Systems

Modeling HBM2 Memory Controller

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads

A Case Against Hardware Managed DRAM Caches for NVRAM based Systems

Investigating Hardware Caches for Terabyte-scale NVDIMMs

AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming

Filtering Translation Bandwidth with Virtual Caching

When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads

Supporting x86-64 address translation for 100s of GPU lanes

Heterogeneous system coherence for integrated CPU-GPU systems

Funding

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Funding