Simulation Research and gem5
The gem5 simulator is an open source computer architecture simulator used in academia and in industry. gem5 has been under development for at least 15 years initially at the University of Michigan as the m5 project and at the University of Wisconsin as the GEMS project. Since the merger of m5 and GEMS in 2011, gem5 has been cited by over 4800 publications. gem5 is also used by many industrial research labs including ARM Research, AMD Research, Google, Micron, Metempsy, HP, Samsung, and others. The canonical citation for gem5 is now the gem5-20 paper
Professor Jason Lowe-Power is a the chair of gem5’s project management committee and a contributor to gem5. gem5 is heavily used by the DArchR lab to investigate heterogeneous memory, security, and other projects.
The DArchR group is leading the RE-gem5 project. RE-gem5 is a directed effort to rejuvenate the underlying infrastructure of gem5. RE-gem5 is not a new simulator or a new project; it is a project to enhance and support the current gem5 infrastructure. We are embarking on the RE-gem5 project to reinvigorate the gem5 infrastructure to enable the next 15 years of computer architecture research. This project will enhance and rejuvenate the aging gem5 community infrastructure through improvements to the underlying gem5 components, community outreach and improved user services, and developing new models for emerging devices required for evaluating important applications. This project will create a sustainable path for the future of the gem5 infrastructure by improving the code testing coverage and increasing the robustness of hardware device models. Additionally, community outreach efforts will broaden the community, increasing the impact of gem5 and providing more contributors to continue development of this infrastructure after this project completes.
Related publications
Potential and Limitation of High-Frequency Cores and Caches
Kunal Pai, Anusheel Nand, Jason Lowe-Power. ModSim 2024: Workshop on Modeling & Simulation of Systems and Applications.
Validating Hardware and SimPoints with gem5: A RISC-V Board Case Study
Kunal Pai, Zhantong Qiu, Jason Lowe-Power. ISCA 2023: gem5 Workshop.
HammerSim: A Tool to Model Rowhammer
Kaustav Goswami, Ayaz Akram, Hari Venugopalan, Jason Lowe-Power, Young Architect Workshop at ASPLOS 2023.
Enabling Design Space Exploration for RISC-V Secure Compute Environments
Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021). With ISCA 2021.
How to develop a bad research tool
Jason Lowe-Power. 2021 Workshop on Negative results, Opportunities, Perspectives, and Experiences (NOPE 2021). Held with ASPLOS. 2021
Enabling reproducible and agile full-system simulation
Best paper nominee Bobby R. Bruce, Ayaz Akram, Hoa Nguyen, Kyle Roarty, Mahyar Samani, Marjan Fariborz, Trivikram Reddy, Matthew D. Sinclair, Jason Lowe-Powe...
FlexCPU: A Configurable Out-of-Order CPU Abstraction
Bradley Wang, Ayaz Akram, Jason Lowe-Power ISPASS 2019.
Integrating Cycle Accurate Chisel Models with gem5’s System Simulation
Nima Ganjehloo, Jason Lowe-Power, Venkatesh Akella. CCC 2018.
gem5-gpu: A Heterogeneous CPU-GPU Simulator
Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill and David A. Wood. Computer Architecture Letters 2014.
Funding
Our gem5 work has been generously supported by the following sponsors:
The gem5 simulator is proudly a CISE Community Research Infrastructure (CCRI) through CNS-1925724. Click here for other CCRI-funded infrastructures.
The gem5 project has also been supported by NSF CSR-1850566 and gem5 is also sponsored by Google.