gem5 is an open source computer architecture simulator used in academia and in industry. gem5 has been under development for at least 15 years initially at the University of Michigan as the m5 project and at the University of Wisconsin as the GEMS project. Since the merger of m5 and GEMS in 2011, gem5 has been cited by over 2600 publications. gem5 is also used by many industrial research labs including ARM Research, AMD Research, Google, Micron, Metempsy, HP, Samsung, and others.
Professor Jason Lowe-Power is a member of gem5’s project management committee and a contributor to gem5. gem5 is heavily used by the DArchR lab to investigate heterogeneous memory, security, and other projects.
Below are a number of gem5 projects that are either ongoing or that we are looking for enthusiastic students to work on. I am currently looking for motivated students to work on these projects. If you are currently a student at UC Davis, email Jason (email@example.com) to set up a meeting to find out more information about these projects. Most of these projects are a good size for a Master’s project. However, many can also be extended into a Master’s thesis or larger project. Also, if you are interested in applying to the UC Davis PhD program, working on one of these projects ahead of time would be very impressive. Contributing to a large open source project like gem5 is also a great resume booster! All of these project will result in commits to upstream gem5.
Improve gem5 testing infrastructure
gem5 has a new testing infrastructure. However, most of the old tests have not been ported to the new infrastructure, yet. In this project, you will increase the test coverage of gem5.
This project will have huge impact on the gem5 community by improving the codebase. This project required Python knowledge since the testing infrastructure is implemented in Python, and C/C++ knowledge as well. You will be porting tests from the old testing infrastructure as well as developing new tests from scratch. One example type of new test is described below.
X86 instruction tests
Write some simple tests that check to make sure the x86 instructions are implemented correctly. https://github.com/benchmark-subsetting/cere could be helpful. gem5 can simulate many different ISAs (x86, ARM, RISC-V, and others). However, the ISA implementations have not been rigorously publicly tested. Now that we have a new testing infrastructure, adding tests to make sure the ISA is correctly implemented is a high priority.
One of the key purposes of gem5 is to get statistics on the system performance and other information (e.g., cache misses). Currently, the stats are dumped into a poorly formatted text file. This text file is large, hard to parse, and difficult to use dynamically. The stats code inside gem5 seems like it should be flexible, but turns out to be pretty rigid. This project would revamp the stats to be much more flexible to allow different kinds of output (text file, database, pandas, other) and allow you to access the stats from gem5’s python run scripts. Going beyond this first step, we can also look into providing stats for gem5’s KVM native execution engine and trying to match hardware performance counters with gem5’s stats.
Not only is hardware technology changing rapidly, but the workloads that execute on this hardware are also evolving. A few examples include machine learning, augmented reality, big-data analytics, and intelligent personal assistants. These applications are end-to-end solutions, consisting of many interacting kernels of computation, and they cannot easily or accurately be represented as a single microbenchmark. Optimizing these applications requires changes across the entire hardware-software stack from new accelerators and emerging programmable processors to system integration and new programming interfaces. However, current architecture evaluation infrastructure is not easily adapted to studying end-to-end applications.
This project will develop in situ simulation to study applications in their native execution environment. We are currently extending gem5 to include in situ support for studying CPUs by leveraging ubiquitous hardware virtualization technology. Looking forward, this virtualization can be extended to other accelerators, programmable processors, and even to novel devices via fast emulation (e.g., with FPGAs).
Improve KVM support
Using KVM (kernel virtual machine) allows us to use the actual hardware as the CPU “model”. This means gem5 can run at native speed (compared to the usual 10,000-1,000,000x slowdown). However, much of this was cobbled together and needs to be updated to work on both AMD and Intel platforms. There are a number of patches floating around, but no one really understands what they do and/or what in the patches are needed. It would be great to test this support on both Intel and AMD systems and try to get these patches checked in. Assuming that goes well, there’s a bunch of other KVM-related features that I would like to implement. This project will dig into some Linux kernel nitty-gritty and will require reading and understand a lot of complicated code (much of which I don’t understand myself :)).
Network support for KVM
I want to be able to do “apt install” inside KVM and to connect to other services/servers. This is a great first step toward in situ simulation.
Display support for KVM
I would like to see “real” support, but even revamping the VNC code would be a good start. This is likely a huge project.
Make a new CPU model that can more flexibly do memory-level parallelism. The idea is to “speculate perfectly.” You could execute the instructions (branches, loads, etc.) functionally, and know that the load value or the branch direction is correct. Just wait until the end to commit it. The goal would be to specify parameters at a higher level than “ROB size” or “LSQ size” or number of pipeline stages. Then, you could tune the performance to what you want. This would be useful when you don’t care about the core microarchitecture, you just want a high-performance CPU. Also, you could use it for limit studies to compare against. It would also be cool if you could model different microarchitectures with it. E.g., can you model AMD and Intel by tuning the parameters correctly? At least a high level?
gem5 simulation for Verilog/CHISEL
This needs to be filled in.
Get workloads running in gem5
What are the important workloads we want to look at?
- Node.js for server
- Python tests?
- Check the phoronix benchmark suite
GUI for gem5
I was down on this before, but maybe it will open up research to more people. Visualizing things is always good, right?
Design and configure the system in a GUI. Basically, you could replace the python config files with a GUI.
Smaller ideas for gem5 improvements
Replace Ruby’s cache models (
DirectoryMemory, etc.) with models using the “classic” cache code. I think Daniel Carvalho’s updates to the replacement policies, etc. should make it very easy for us to do this. This change would be a huge step towards unifying Ruby and the classic caches.
Automate the process of creating checkpoints with gem5 for the required workloads.
Make CPU interrupts more fully event driven instead of requiring polling by adding listeners for the Interrupts::post(int,int) function, or BaseCPU::postInterrupt(int,int,int). Whichever is more sensible.