NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing
Marjan Fariborz, Mahyar Samani, Austin York, SJ Ben Yoo, Jason Lowe-Power, Venkatesh Akella
TDRAM: Tag-enhanced DRAM for Efficient Caching
Maryam Babaie, Ayaz Akram, Wendy Elsasser, Brent Haukness, Michael R. Miller, Taeksang Song, Thomas Vogelsang, Steven C. Woo, Jason Lowe-Power
Potential and Limitation of High-Frequency Cores and Caches
Kunal Pai, Anusheel Nand, Jason Lowe-Power. ModSim 2024: Workshop on Modeling & Simulation of Systems and Applications.
CachedArrays: Optimizing Data Movement for Heterogeneous Memory Systems
Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella. IPDPS 2024
TEGRA – Scaling Up Terascale Graph Processing with Disaggregated Computing
William Shaddix, Mahyar Samani, Marjan Fariborz, S.J. Ben Yoo, Jason Lowe-Power, Venkatesh Akella
Aragorn: A Privacy-Enhancing System for Mobile Cameras
Hari Venugopalan, Zainul Abi Din, Trevor Carpenter, Jason Lowe-Power, Samuel T. King, and Zubair Shafiq. IMWUT 2024.
Centauri: Practical Rowhammer Fingerprinting
Hari Venugopalan, Kaustav Goswami, Zainul Abi Din, Jason Lowe-Power, Samuel T. King, Zubair Shafiq
Validating Hardware and SimPoints with gem5: A RISC-V Board Case Study
Kunal Pai, Zhantong Qiu, Jason Lowe-Power. ISCA 2023: gem5 Workshop.
Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems
Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella High Performance Computing: 38th International Conference, ISC High Performance 2023.
HammerSim: A Tool to Model Rowhammer
Kaustav Goswami, Ayaz Akram, Hari Venugopalan, Jason Lowe-Power, Young Architect Workshop at ASPLOS 2023.
Validating gem5’s Memory Components
Mahyar Samani, Jason Lowe-Power, gem5 workshop at ISCA 2022.
Rethinking the Management Techniques in Emerging Memory Systems
Maryam Babaie, Ayaz Akram, Jason Lowe-Power MICRO 2022: The 8th CWIDCA Workshop.
Toward High-Fidelity Heterogeneous Memory System Modeling in gem5
Maryam Babaie, Ayaz Akram, Jason Lowe-Power ModSim 2022: Workshop on Modeling & Simulation of Systems and Applications
A Cycle-level Unified DRAM Cache Controller Model in gem5
Maryam Babaie, Ayaz Akram, Jason Lowe-Power ISCA 2022: The 4th gem5 Tutorial and User’s Workshop.
A Model for Scalable and Balanced Accelerators for Graph Processing
Mark Hildebrand, Jason Lowe-Power, and Venkatesh Akella. International Conference on High Performance Computing. 2023.
SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems
Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022.
Modeling HBM2 Memory Controller
Ayaz Akram, Maryam Babaie, Wendy Elsasser, Jason Lowe-Power. The 4th gem5 Users’ Workshop associated with ISCA 2022.
LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads
Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-min yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, S. J. Ben Yoo ISC-HPC 2022.
HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads
Pouya Fotouhi, Marjan Fariborz, Roberto Proietti, Jason Lowe-Power, Venkatesh Akella, S. J. Ben Yoo ISC-HPC 2021.
Enabling Design Space Exploration for RISC-V Secure Compute Environments
Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021). With ISCA 2021.
Performance Analysis of Scientific Computing Workloads on General Purpose TEEs
Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert. 35th IEEE International Parallel & Distributed Processing Symposium (IPDPS ...
How to develop a bad research tool
Jason Lowe-Power. 2021 Workshop on Negative results, Opportunities, Perspectives, and Experiences (NOPE 2021). Held with ASPLOS. 2021
A Case Against Hardware Managed DRAM Caches for NVRAM based Systems
Best paper nominee Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella 2021 IEEE International Symposium on Performance Analysis of System...
Enabling reproducible and agile full-system simulation
Best paper nominee Bobby R. Bruce, Ayaz Akram, Hoa Nguyen, Kyle Roarty, Mahyar Samani, Marjan Fariborz, Trivikram Reddy, Matthew D. Sinclair, Jason Lowe-Powe...
Investigating Hardware Caches for Terabyte-scale NVDIMMs
Julian T. Angeles, Mark Hildebrand, Venkatesh Akella, Jason Lowe-Power 12TH Annual Non-volatile Memories Workshop (NVMW 2021) 2021.
HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems
Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew Farrens, Venkatesh Akella. ICPP 2020.
AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming
Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella 25th International Conference on Architectural Support for Programming Languages and Operating Systems (...
Using Trusted Execution Environments on High Performance Computing Platforms
Ayaz Akram and Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert Open-source Enclaves Workshop (OSEW 2019) 2019.
The Davis In-Order (DINO) CPU: A Teaching-focused RISC-V CPU Design
Jason Lowe-Power and Christopher Nitta Workshop on Computer Architecture Education (WCAE) 2019.
FlexCPU: A Configurable Out-of-Order CPU Abstraction
Bradley Wang, Ayaz Akram, Jason Lowe-Power ISPASS 2019.
Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP
Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew Farrens, and Venkatesh Akella. HiPC 2018.
Integrating Cycle Accurate Chisel Models with gem5’s System Simulation
Nima Ganjehloo, Jason Lowe-Power, Venkatesh Akella. CCC 2018.
A Case for Exposing Extra-Architectural State in the ISA
Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, and Christopher J. Nitta. HASP Workshop with ISCA 2018.
Filtering Translation Bandwidth with Virtual Caching
Hongil Yoon, Jason Lowe-Power, Gurindar S. Sohi. ASPLOS 2018.
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing
Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew Farrens, Venkatesh Akella. ICCD 2018.
When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads
Jason Lowe-Power, Mark D. Hill, David A. Wood. BPOE Workshop with ASPLOS 2016.
Border Control: Sandboxing Accelerators
Lena E. Olson, Jason Lowe-Power, Mark D. Hill, David A. Wood MICRO 2015.
Implications of Emerging 3D GPU Architecture on the Scan Primitive
Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood. SIGMOD Record 2015.
Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries
Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, David A. Wood. DaMoN (with SIGMOD) 2015.
gem5-gpu: A Heterogeneous CPU-GPU Simulator
Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill and David A. Wood. Computer Architecture Letters 2014.
Supporting x86-64 address translation for 100s of GPU lanes
Jason Power, Mark D. Hill,, David A. Wood. HPCA 2014.
Heterogeneous system coherence for integrated CPU-GPU systems
Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood MICRO 2013.